TL_RX_POSTED_FROM_RAM_READ_PIPELINE (CPM5_PCIE_ATTR) Register Description
Register Name | TL_RX_POSTED_FROM_RAM_READ_PIPELINE |
---|---|
Relative Address | 0x00000005C4 |
Absolute Address |
0x00FCE085C4 (CPM5_PCIE0_ATTR) 0x00FCE885C4 (CPM5_PCIE1_ATTR) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Posted RAM To TL Read Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on rdata. FALSE indicates that there is no pipeline. |
This register should only be written to during reset of the PCIe block
TL_RX_POSTED_FROM_RAM_READ_PIPELINE (CPM5_PCIE_ATTR) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
attr | 0 | rwNormal read/write | 0x0 | Posted RAM To TL Read Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on rdata. FALSE indicates that there is no pipeline. |