| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:4 | rwNormal read/write | 0x0 | Asserting this resets the NIU in the switch corresponding to the Master mentioned above. It needs to be ensured that when this reset is asserted, the respective Master also get reset to ensure error free flow once reset gets released |
| raw_rst_n | 3 | rwNormal read/write | 0x1 | Asserting this resets the NIU in the switch corresponding to the Master mentioned above. It needs to be ensured that when this reset is asserted, the respective Master also get reset to ensure error free flow once reset gets released |
| power_idlereq | 2 | rwNormal read/write | 0x0 | Writing 1b1 initiates a Master isolation request to the corresponding MERB. |
| power_idleack | 1 | roRead-only | 0x1 | 1b1 indicates idle request has been detected. 1b0 indicates idle request has not been detected. NIU reset needs to be enabled to clear this bit. |
| power_idle | 0 | roRead-only | 0x1 | 1b1 indicates master has been isolated. 1b0 indicates master has not been isolated. The reset needs to be asserted to clear this bit. |