| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:20 | roRead-only | 0x0 | Reserved |
| pfifo_overflow | 19 | wtcReadable, write a 1 to clear | 0x0 | Indicates that the Root Port PM_PME FIFO overflowed and a PM_PME message was dropped. Writing a 1 clears the overflow status. |
| pfifo_not_empty | 18 | roRead-only | 0x0 | Indicates that the Root Port PM_PME FIFO has data to read. |
| efifo_overflow | 17 | wtcReadable, write a 1 to clear | 0x0 | Indicates that the Root Port Error FIFO overflowed and an error message was dropped. Writing a 1 clears the overflow status. |
| efifo_not_empty | 16 | roRead-only | 0x0 | Indicates that the Root Port Error FIFO has data to read. |
| Reserved | 15:9 | roRead-only | 0x0 | Reserved |
| pcie_cfg_overwrite | 8 | rwNormal read/write | 0x0 | When set, allows the writes to the RW1C bits in PCIe Configuration Space Header to be overwritten. |
| Reserved | 7:1 | roRead-only | 0x0 | Reserved |
| bdg_en | 0 | rwNormal read/write | 0x0 | When set, allows the reads and writes to the AXIBARs to be presented on the PCIe bus. Root Port software needs to write a 1 to this bit when enumeration is done. PCIe AXI Bridge clears this location when link up to link down transition occurs. |