TZ_DMA1_2 (CPM5_SLCR_SECURE) Register Description
| Register Name | TZ_DMA1_2 |
|---|---|
| Relative Address | 0x000000011C |
| Absolute Address | 0x00FCDE011C (CPM5_SLCR_SECURE) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0xFFFFFFFF |
| Description | TrustZone Classification for PCIe DMA1 1: Non-Secure 0: Secure |
This register should only be written to while the target block is in reset.
TZ_DMA1_2 (CPM5_SLCR_SECURE) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_dma_sec_vf_pf15 | 31 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF15 VF |
| attr_dma_sec_vf_pf14 | 30 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF14 VF |
| attr_dma_sec_vf_pf13 | 29 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF13 VF |
| attr_dma_sec_vf_pf12 | 28 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF12 VF |
| attr_dma_sec_vf_pf11 | 27 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF11 VF |
| attr_dma_sec_vf_pf10 | 26 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF10 VF |
| attr_dma_sec_vf_pf9 | 25 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF9 VF |
| attr_dma_sec_vf_pf8 | 24 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF8 VF |
| attr_dma_sec_vf_pf7 | 23 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF7 VF |
| attr_dma_sec_vf_pf6 | 22 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF6 VF |
| attr_dma_sec_vf_pf5 | 21 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF5 VF |
| attr_dma_sec_vf_pf4 | 20 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF4 VF |
| attr_dma_sec_vf_pf3 | 19 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF3 VF |
| attr_dma_sec_vf_pf2 | 18 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF2 VF |
| attr_dma_sec_vf_pf1 | 17 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF1 VF |
| attr_dma_sec_vf_pf0 | 16 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF0 VF |
| attr_dma_sec_pf15 | 15 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF15 |
| attr_dma_sec_pf14 | 14 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF14 |
| attr_dma_sec_pf13 | 13 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF13 |
| attr_dma_sec_pf12 | 12 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF12 |
| attr_dma_sec_pf11 | 11 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF11 |
| attr_dma_sec_pf10 | 10 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF10 |
| attr_dma_sec_pf9 | 9 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF9 |
| attr_dma_sec_pf8 | 8 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF8 |
| attr_dma_sec_pf7 | 7 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF7 |
| attr_dma_sec_pf6 | 6 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF6 |
| attr_dma_sec_pf5 | 5 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF5 |
| attr_dma_sec_pf4 | 4 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF4 |
| attr_dma_sec_pf3 | 3 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF3 |
| attr_dma_sec_pf2 | 2 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF2 |
| attr_dma_sec_pf1 | 1 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF1 |
| attr_dma_sec_pf0 | 0 | rwNormal read/write | 0x1 | multiq AXIMM A*PROT setting for PF0 |