ISR (PMC_IOP_SLCR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

ISR (PMC_IOP_SLCR) Register Description

Register NameISR
Relative Address0x0000000800
Absolute Address 0x00F1060800 (PMC_IOP_SLCR)
Width 1
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterrupt Status Register

This is a sticky register that holds the value of the interrupt until cleared by a value of 1. Alternate register name: isr

ISR (PMC_IOP_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0wtcReadable, write a 1 to clear0x0Status for an address decode error.
0: No Event
1: Event Occurred