ps_dma_axi_lpd_wr_I_main_QosGenerator_Priority (LPD_INT_GPV) Register Description
Register Name | ps_dma_axi_lpd_wr_I_main_QosGenerator_Priority |
Relative Address | 0x0000000088 |
Absolute Address |
0x00FE400088 (LPD_INT_GPV)
|
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x80000700 |
Description | Priority register. |
Alternate register name: if_adma_intlpd_axi_wr_I_main_QosGenerator_Priority
ps_dma_axi_lpd_wr_I_main_QosGenerator_Priority (LPD_INT_GPV) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
MARK | 31 | roRead-only | 0x1 | Backward compatibility marker when 0. |
P1 | 10:8 | rwNormal read/write | 0x7 | In Regulator mode, defines the HIGH hurry level. In Fixed/Limiter mode, defines the Urgency level for READ transactions. |
P0 | 2:0 | rwNormal read/write | 0x0 | In Regulator mode, defines the LOW hurry level. In Fixed/Limiter mode, defines the Urgency level for WRITE transactions. |