ADV_SWTm_MSIX_CAP_TABLE_SIZE_15 (CPM5_PCIE_ATTR) Register Description
| Register Name | ADV_SWTm_MSIX_CAP_TABLE_SIZE_15 |
|---|---|
| Relative Address | 0x00000026B4 |
| Absolute Address |
0x00FCE0A6B4 (CPM5_PCIE0_ATTR) 0x00FCE8A6B4 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic. |
This register should only be written to during reset of the PCIe block
ADV_SWTm_MSIX_CAP_TABLE_SIZE_15 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 10:0 | rwNormal read/write | 0x0 | MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does not implement the table; that must be implemented in user logic. |