SIGCOMP0_127_96 (DBG_ELA_256) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

SIGCOMP0_127_96 (DBG_ELA_256) Register Description

Register NameSIGCOMP0_127_96
Relative Address0x000000018C
Absolute Address 0x00F0F4018C (DBG_CPM_ELA2A)
0x00F0F5018C (DBG_CPM_ELA2B)
0x00F0F6018C (DBG_CPM_ELA2C)
0x00F0F7018C (DBG_CPM_ELA2D)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionSIGCOMP0[127:96]

SIGCOMP0_127_96 (DBG_ELA_256) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SIGCOMP031:0rwNormal read/write0Signal Comparison value