PCIE1_SMID_CFG0 (CPM5_SLCR_SECURE) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID: AM012
Release Date: 2023-08-29
Revision: 1.3

PCIE1_SMID_CFG0 (CPM5_SLCR_SECURE) Register Description

Register Name	PCIE1_SMID_CFG0
Relative Address	0x0000000210
Absolute Address	0x00FCDE0210 (CPM5_SLCR_SECURE)
Width	32
Type	rwNormal read/write
Reset Value	0x76543210
Description	SMID configuration for PCIe/DMA AXI Master 1 Interface to non coherent interconnect

PCIE1_SMID_CFG0 (CPM5_SLCR_SECURE) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
bdf_bit_sel_7	31:28	rwNormal read/write	0x7	Determines which BDF bit drives SMID bit 7
bdf_bit_sel_6	27:24	rwNormal read/write	0x6	Determines which BDF bit drives SMID bit 6
bdf_bit_sel_5	23:20	rwNormal read/write	0x5	Determines which BDF bit drives SMID bit 5
bdf_bit_sel_4	19:16	rwNormal read/write	0x4	Determines which BDF bit drives SMID bit 4
bdf_bit_sel_3	15:12	rwNormal read/write	0x3	Determines which BDF bit drives SMID bit 3
bdf_bit_sel_2	11:8	rwNormal read/write	0x2	Determines which BDF bit drives SMID bit 2
bdf_bit_sel_1	7:4	rwNormal read/write	0x1	Determines which BDF bit drives SMID bit 1
bdf_bit_sel_0	3:0	rwNormal read/write	0x0	Determines which BDF bit drives SMID bit 0