LL_ACK_TIMEOUT_FUNC (CPM5_PCIE_ATTR) Register Description
| Register Name | LL_ACK_TIMEOUT_FUNC |
|---|---|
| Relative Address | 0x00000004EC |
| Absolute Address |
0x00FCE084EC (CPM5_PCIE0_ATTR) 0x00FCE884EC (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Defines how LL_ACK_TIMEOUT is to be used, if enabled with LL_ACK_TIMEOUT_EN (otherwise, this is not used). 0 = No Effect 1 = Add LL_ACK_TIMEOUT to the built-in table value. 2 = Subtract LL_ACK_TIMEOUT from the built-in table value. Here LL_ACK_TIMEOUT value should follow the following rules: a) For any Width, Gen1/2/3/4 speed iff MPS > 512B: Allowed Range is 1 <= RANGE <= 64d b) For any Width, Gen1/2/3/4 speed iff MPS <= 512B: Allowed Range is 1 <= RANGE <= 32d |
This register should only be written to during reset of the PCIe block
LL_ACK_TIMEOUT_FUNC (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 1:0 | rwNormal read/write | 0x0 | Defines how LL_ACK_TIMEOUT is to be used, if enabled with LL_ACK_TIMEOUT_EN (otherwise, this is not used). 0 = No Effect 1 = Add LL_ACK_TIMEOUT to the built-in table value. 2 = Subtract LL_ACK_TIMEOUT from the built-in table value. Here LL_ACK_TIMEOUT value should follow the following rules: a) For any Width, Gen1/2/3/4 speed iff MPS > 512B: Allowed Range is 1 <= RANGE <= 64d b) For any Width, Gen1/2/3/4 speed iff MPS <= 512B: Allowed Range is 1 <= RANGE <= 32d |