DMA_Config (GEM) Register Description
| Register Name | DMA_Config |
|---|---|
| Relative Address | 0x0000000010 |
| Absolute Address |
0x00FF0C0010 (GEM0) 0x00FF0D0010 (GEM1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00020784 |
| Description | DMA Configuration |
Alternate register name: dma_config
DMA_Config (GEM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| dma_addr_bus_width_1 | 30 | rwNormal read/write | 0x0 | DMA address bus width. 0 = 32b, 1 = 64b. |
| tx_bd_extended_mode_en | 29 | rwNormal read/write | 0x0 | Enable RX extended BD mode. See tx_bd_control register definition for description of feature. |
| rx_bd_extended_mode_en | 28 | rwNormal read/write | 0x0 | Enable RX extended BD mode. See rx_bd_control register definition for description of feature. |
| Reserved | 27 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| force_max_amba_burst_tx | 26 | rwNormal read/write | 0x0 | Force max length bursts on TX. Force the TX DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers as defined by bits 4:0 of this register, even when there is less than max burst data bytes to read. Residual data read is ignored. AHB only - does not apply on AXI bursts (prior to release 1p10) or bursts that break 1k boundary rule - supported on AXI from release 1p10. |
| force_max_amba_burst_rx | 25 | rwNormal read/write | 0x0 | Force max length bursts on RX. Force the RX DMA to always issue max length bursts on EOP (end of packet) or EOB (end of buffer) transfers, even if there is less than max burst real packet data required to write. Any extra bytes of pad data is set to 0x00. AHB only - does not apply on AXI bursts (prior to release 1p10) or bursts that break 1k boundary rule - supported on AXI from release 1p10. |
| force_discard_on_err | 24 | rwNormal read/write | 0x0 | Auto Discard RX frames during lack of resource. When set, the GEM DMA will automatically discard receive packets from the receiver packet buffer memory when no AMBA (AHB/AXI) resource is available. When low, then received packets will remain to be stored in the SRAM based packet buffer until AMBA (AHB/AXI) buffer resource next becomes available. A write to this bit is ignored if the DMA is not configured in the packet buffer full store and forward mode. |
| rx_buf_size | 23:16 | rwNormal read/write | 0x2 | DMA receive buffer size in external AMBA (AHB/AXI) system memory. The value defined by these bits determines the size of buffer to use in main system memory when writing received data. The value is defined in multiples of 64 bytes.0x01 corresponds to buffers of 64 bytes0x02 corresponds to 128 bytes etc.For example:0x02: 128 byte.0x18: 1536 byte (1*max length frame/buffer)0xA0: 10240 byte (1*10K jumbo frame/buffer)Note that this value should never be written as zero.Note. The reset value of this field is equal to the gem_rx_buffer_length_def define, which is user configurable. |
| Reserved | 15:14 | roRead-only | 0x0 | Reserved, read as 0, ignored on write. |
| crc_error_report | 13 | rwNormal read/write | 0x0 | When the bit is set, bit 16 of the receive buffer descriptor will represent FCS/CRC error (only if frames with FCS are copied to memory as enabled by bit 26 in the network config register). When this bit is clear, bit 16 of the receive buffer descriptor will represent the Canonical format indicator (CFI) bit as extracted from the receive frame (if the receive buffer descriptor is pointing to the last data buffer of the receive frame and the received frame was VLAN tagged). |
| infinite_last_dbuf_size_en | 12 | rwNormal read/write | 0x0 | Forces the receive DMA to consider the data buffer pointed to by last descriptor in the descriptor list to be of elastic size (the last descriptor is the one with its wrap bit set). This means the first buffer pointed to in the list will always contain the beginning of a frame (this helps if there is a desire to build custom logic that interfaces with the receive buffer directly without software intervention). When set the rx_buf_size bits 23:16 in the dma configuration register are ignored for the last receive buffer in the descriptor list and data will be written into the buffer sequentially until the frame is completely received and the buffer descriptor status will be updated with the frame length as normal. |
| tx_pbuf_tcp_en | 11 | rwNormal read/write | 0x0 | Transmitter IP, TCP and UDP checksum generation offload enable (not supported when in TX Partial Store and Forward mode). When set, the transmitter checksum generation engine is enabled, to calculate and substitute checksums for transmit frames. When clear, frame data is unaffected. If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as 0, ignored on write. |
| tx_pbuf_size | 10 | rwNormal read/write | 0x1 | Transmitter packet buffer memory size select. Having this bit at zero halves the amount of memory used for the transmit packet buffer. This reduces the amount of memory used by the GEM. It is important to set this bit to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 4 Kbytes.1: Use full configured addressable space (4 Kb)0: Do not use top address bit (2 Kb)If the GEM is not configured to use the DMA packet buffer, this bit is not implemented and will be treated as reserved, read as 0, ignored on write.Note. The reset value of this field is equal to the gem_tx_pbuf_size_def define, which is user configurable. |
| rx_pbuf_size | 9:8 | rwNormal read/write | 0x3 | Receiver packet buffer memory size select. Having these bits at less than 11 reduces the amount of memory used for the receive packet buffer. This reduces the amount of memory used by the GEM. It is important to set these bits both to one if the full configured physical memory is available. The value in brackets below represents the size that would result for the default maximum configured memory size of 8 Kbytes.11: Use full configured addressable space (8 Kb)10: Do not use top address bit (4 Kb)01: Do not use top two address bits (2 Kb)00: Do not use top three address bits (1 Kb)If the GEM is not configured to use the DMA packet buffer, these bits are not implemented and will be treated as reserved, read as 0, ignored on write.Note. The reset value of this field is equal to the gem_rx_pbuf_size_def define, which is user configurable. |
| endian_swap_packet | 7 | rwNormal read/write | 0x1 | endian swap mode enable for packet data accesses. When set, selects swapped endianism for AMBA (AHB/AXI) transfers. When clear, selects little endian mode. |
| endian_swap_management | 6 | rwNormal read/write | 0x0 | endian swap mode enable for management descriptor accesses. When set, selects swapped endianism for AMBA (AHB/AXI) transfers. When clear, selects little endian mode. |
| hdr_data_splitting_en | 5 | rwNormal read/write | 0x0 | Enable header data Splitting. When set, receive frames will be forwarded to main memory using a minimum of two DMA data buffers. The first X data buffers will contain the frame header, consisting of the Ethernet,VLAN,(IPv4 or IPv6),(TCP or UDP). X= (frame header size divided by rx_buf_size as defined in bits 23:16 of this register). The last Y data buffers will contain the frame payload. Y= (frame payload size divided by rx_buf_size). Note that for non VLAN/IP/TCP/UDP frames, the header will always be 14 bytes. When this feature is disabled, the frame is forwarded to main memory in blocks of rx_buf_size. |
| amba_burst_length | 4:0 | rwNormal read/write | 0x4 | Tx data frame DMA burst length on AXI master. One-hot priority encoding (x represents dont care): 1xxxx: Attempt to use bursts of up to 16. 01xxx: Attempt to use bursts of up to 8. 001xx: Attempt to use bursts of up to 4. 0001x: Use single word. 00001: Use single word. 00000: Attempt to use bursts of up to 256. Note: Not used for DMA management operations. Note: Only used where space and data size allow and respecting AXI burst boundary rules. |