TRCITCTRL (DBG_A720_ETM) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

TRCITCTRL (DBG_A720_ETM) Register Description

Register NameTRCITCTRL
Relative Address0x0000000F00
Absolute Address 0x00F0D30F00 (DBG_APU0_ETM)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionIntegration Mode Control Register

TRCITCTRL (DBG_A720_ETM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
IME 0rwNormal read/write0x0Integration mode enable bit