MATCH3_CNT1 (TTC) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

MATCH3_CNT1 (TTC) Register Description

Register NameMATCH3_CNT1
Relative Address0x0000000048
Absolute Address 0x00FF0E0048 (TTC0)
0x00FF0F0048 (TTC1)
0x00FF100048 (TTC2)
0x00FF110048 (TTC3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMatch value

Alternate register name: Match_3_Counter_1

MATCH3_CNT1 (TTC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Match31:0rwNormal read/write0x0When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers.