PL_ENABLE_CCIX_EDR (CPM4_PCIE1_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PL_ENABLE_CCIX_EDR (CPM4_PCIE1_ATTR) Register Description

Register NamePL_ENABLE_CCIX_EDR
Relative Address0x00000002E0
Absolute Address 0x00FCA602E0 (CPM4_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEnable CCIX EDR mode.

This register should only be written to during reset of the PCIe block

PL_ENABLE_CCIX_EDR (CPM4_PCIE1_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0Enable CCIX EDR mode.