PFx_MSI_CAP_NEXTPTR_10 (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PFx_MSI_CAP_NEXTPTR_10 (CPM5_PCIE_ATTR) Register Description

Register NamePFx_MSI_CAP_NEXTPTR_10
Relative Address0x0000000EA4
Absolute Address 0x00FCE08EA4 (CPM5_PCIE0_ATTR)
0x00FCE88EA4 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMSI Capability Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.

This register should only be written to during reset of the PCIe block

PFx_MSI_CAP_NEXTPTR_10 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 7:0rwNormal read/write0x0MSI Capability Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability.