SMMU_CB25_TLBSYNC (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

SMMU_CB25_TLBSYNC (FPD_SMMU_TCU) Register Description

Register NameSMMU_CB25_TLBSYNC
Relative Address0x00000397F0
Absolute Address 0x00FD8397F0 (FPD_SMMU_TCU)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInitiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.

SMMU_CB25_TLBSYNC (FPD_SMMU_TCU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bits31:0woWrite-only0x0Initiates a synchronization operation that ensures the completion of any TLB invalidate operations previously accepted in the corresponding translation context bank.