SMMU_NSACR (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

SMMU_NSACR (FPD_SMMU_TCU) Register Description

Register NameSMMU_NSACR
Relative Address0x0000000410
Absolute Address 0x00FD800410 (FPD_SMMU_TCU)
Width32
TyperwNormal read/write
Reset Value0x0400001C
DescriptionProvides IMPLEMENTATION DEFINED functionality.

SMMU_NSACR (FPD_SMMU_TCU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CACHE_LOCK26rwNormal read/write0x1Provides IMPLEMENTATION DEFINED functionality.
DP4K_TBUDISB25rwNormal read/write0x0Provides IMPLEMENTATION DEFINED functionality.
DP4K_TCUDISB24rwNormal read/write0x0Provides IMPLEMENTATION DEFINED functionality.
S2CRB_TLBEN10rwNormal read/write0x0Provides IMPLEMENTATION DEFINED functionality.
MMUDISB_TLBEN 9rwNormal read/write0x0Provides IMPLEMENTATION DEFINED functionality.
SMTNMB_TLBEN 8rwNormal read/write0x0Provides IMPLEMENTATION DEFINED functionality.
IPA2PA_CEN 4rwNormal read/write0x1Provides IMPLEMENTATION DEFINED functionality.
S2WC2EN 3rwNormal read/write0x1Provides IMPLEMENTATION DEFINED functionality.
S1WC2EN 2rwNormal read/write0x1Provides IMPLEMENTATION DEFINED functionality.