PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN5 (CPM5_PCIE_ATTR) Register Description
| Register Name | PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN5 |
|---|---|
| Relative Address | 0x00000003BC |
| Absolute Address |
0x00FCE083BC (CPM5_PCIE0_ATTR) 0x00FCE883BC (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Downstream Port Auto Speed Change to Gen5: When FALSE enable Downstream Port to autonomously change speed to Gen4. When TRUE will require software to issue "link retrain". Usually set to TRUE only to overcome VIP modelling limitations. |
This register should only be written to during reset of the PCIe block
PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN5 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 | Downstream Port Auto Speed Change to Gen5: When FALSE enable Downstream Port to autonomously change speed to Gen4. When TRUE will require software to issue "link retrain". Usually set to TRUE only to overcome VIP modelling limitations. |