GCTL (USB_XHCI) Register Description
| Register Name | GCTL |
|---|---|
| Relative Address | 0x000000C110 |
| Absolute Address | 0x00FE20C110 (USB2_XHCI) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x30C13004 |
| Description | Global Core Control |
Specifies the Global Control Register 1 (GCTL) power-on initialization value.
GCTL (USB_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PWRDNSCALE | 31:19 | rwNormal read/write | 0x618 | Power Down Scale (PwrDnScale) The Power Down Scale field specifies how many suspend_clk periods fit into a 16 kHz clock period. When performing the division, round up the remainder. For example, when using an 8-bit/16-bit/32-bit PHY and 25-MHz Suspend clock, Power Down Scale = 25000 kHz/16 kHz = 13d1563 (rounder up) Note: - Minimum Suspend clock frequency is 32 kHz - Maximum Suspend clock frequency is 125 MHz The LTSSM uses Suspend clock for 12-ms and 100-ms timers during suspend mode. According to the USB 3.0 specification, the accuracy on these timers is 0% to +50%. - 12 ms + 0~+50% accuracy = 18 ms (Range is 12 ms - 18 ms) - 100 ms + 0~+50% accuracy = 150 ms (Range is 100 ms - 150 ms). The suspend clock accuracy requirement is: - (12,000/62.5) * (GCTL[31:19]) * actual suspend_clk_period must be between 12,000 and 18,000 - (100,0000/62.5) * (GCTL[31:19]) * actual suspend_clk_period must be between 100,000 and 150,000 For example, if your suspend_clk frequency varies from 7.5 MHz to 10.5MHz, then the value needs to programmed is: Power Down Scale = 10500/16 = 657 (rounded up; and fastest frequency used). |
| MASTERFILTBYPASS | 18 | rwNormal read/write | 0x0 | Master Filter Bypass When this bit is set to 1b1, all the filters in the DWC_usb3_filter module are bypassed. The double synchronizers to mac_clk preceding the filters are also bypassed. For enabling the filters, this bit must be 1b0. |
| BYPSSETADDR | 17 | rwNormal read/write | 0x0 | Bypass SetAddress in Device Mode. When BYPSSETADDR bit is set, the device core uses the value in the DCFG[DevAddr] bits directly for comparing the device address in the tokens. For simulation, you can use this feature to avoid sending an actual SET ADDRESS control transfer on the USB, and make the device core respond to a new address. When the xHCI Debug capability is enabled and this bit is set, the Debug Target immediately enters the configured state without requiring the Debug Host to send a SetAddress or SetConfig request. Note: You can set this bit for simulation purposes only. In the actual hardware, this bit must be set to 1b0. |
| U2RSTECN | 16 | rwNormal read/write | 0x1 | U2RSTECN If the SuperSpeed connection fails during POLL or LMP exchange, the device connects at non-SS mode. If this bit is set, then device attempts three more times to connect at SS, even if it previously failed to operate in SS mode. For each attempt, the device checks receiver termination eight times. From 2.60a release, this bit controls whether to check for Rx.Detect eight times or one time for every attempt. Device controller on USB 2.0 reset checks for receiver termination eight times per attempt if this bit is set to zero, or only once per attempt if the bit is set to one. Note: This bit is applicable only in device mode. |
| FRMSCLDWN | 15:14 | rwNormal read/write | 0x0 | FRMSCLDWN This field scales down device view of a SOF/USOF/ITP duration. For SS/HS mode: - Value of 2h3 implements interval to be 15.625 us - Value of 2h2 implements interval to be 31.25 us - Value of 2h1 implements interval to be 62.5 us - Value of 2h0 implements interval to be 125us For FS mode, the scale-down value is multiplied by 8. When xHCI Debug Capability is enabled, this field also scales down the MaxPacketSize of the IN and OUT bulk endpoint to allow more traffic during simulation. It can only be changed from a non-zero value during simulation. - 2h0: 1024 bytes - 2h1: 512 bytes - 2h2: 256 bytes - 2h3: 128 bytes |
| PRTCAPDIR | 13:12 | rwNormal read/write | 0x3 | PRTCAPDIR: Port Capability Direction (PrtCapDir) - 2b01: for Host configurations - 2b10: for Device configurations Note: For static Host-only/Device-only applications, use DRD Host or DRD Device mode. The combination of GCTL.PrtCapDir=2b11 with SRP and HNP/RSP disabled is not recommended for these applications. The sequence for switching modes in DRD configuration is as follows: Switching from Device to Host: 1. Reset the controller using GCTL[11] (CoreSoftReset). 2. Set GCTL[13:12] (PrtCapDir) to 2b01 (Host mode). 3. Reset the host using USBCMD.HCRESET. 4. Follow the steps in "Initializing Host Registers" section of the TRM. Switching from Host to Device: 1. Reset the controller using GCTL[11] (CoreSoftReset). 2. Set GCTL[13:12] (PrtCapDir) to 2b10 (Device mode). 3. Reset the device by setting DCTL[30] (CSftRst). 4. Follow the steps in "Register Initialization" section of the TRM. Programming this field with random data causes the controller to keep toggling between the host mode and the device mode. Bit Bash register testing is not recommended. |
| CORESOFTRESET | 11 | rwNormal read/write | 0x0 | Core Soft Reset (CoreSoftReset) - 1b0 - No soft reset - 1b1 - Soft reset to core Clears the interrupts and all the CSRs except the following registers: - GCTL - GUCTL - GSTS - GSNPSID - GGPIO - GUID - GUSB2PHYCFGn registers - GUSB3PIPECTLn registers - DCFG - DCTL - DEVTEN - DSTS When you reset PHYs (using GUBS3PHYCFG or GUSB3PIPECTL registers), you must keep the core in reset state until PHY clocks are stable. This controls the bus, ram, and mac domain resets. Note: This bit is for debug purposes only. Use USBCMD.HCRESET in xHCI Mode and DCTL.SoftReset in device mode for soft reset. Programming this field with random data will reset the internal logic of the host controller. Due to this side effect Bit Bash register testing is not recommended. |
| U1U2TimerScale | 9 | rwNormal read/write | 0x0 | Disable U1/U2 timer Scaledown (U1U2TimerScale). If set to 1 along with GCTL[5:4] (ScaleDown) = 2bX1, disables the scale down of U1/U2 inactive timer values. This is for simulation mode only. |
| DEBUGATTACH | 8 | rwNormal read/write | 0x0 | Debug Attach When this bit is set, - SS Link proceeds directly to the Polling link state (after RUN/STOP in the DCTL register is asserted) without checking remote termination; - Link LFPS polling timeout is infinite; - Polling timeout during TS1 is infinite (in case link is waiting for TXEQ to finish). |
| RAMCLKSEL | 7:6 | rwNormal read/write | 0x0 | RAM Clock Select (RAMClkSel) - 2b00: bus clock - 2b01: pipe clock (Only used in device mode) - 2b10: In device mode , pipe/2 clock.In Host mode, controller switches ram_clk between pipe/2 clock, mac2_clk and bus_clk based on the status of the U2/U3 ports - 2b11: In device mode, selects mac2_clk as ram_clk (when 8-bit UTMI or ULPI used) In Host mode, controller switches ram_clk between pipe_clk, mac2_clk and bus_clk based on the status of the U2/U3 ports. In device mode, upon a USB reset and USB disconnect, the hardware clears these bits to 2b00. Note: - In device mode, if you set RAMClkSel to 2b11 (mac2_clk), the controller internally switches the ram_clk to bus_clk when the link state changes to Suspend (L2 or L3), and switches the ram_clk back to mac2_clk when the link state changes to resume or U2. - In host mode, if a value of 2/3 is chosen, then controller switches ram_clk between bus_clk, mac2_clk and pipe_clk, pipe_clk/2, based on the state of the U2/U3 ports. For example if U2 port is active, then the ram_clk is swicthed to mac2_clk. when all U2 ports are suspended, it switch the ram_clk to bus_clk. This allows de coupling the ram_clk from the bus_clk and depending on the bandwidth requiredmnet allows the bus_clk to be run at a lower frequency than the ram_clk requirements. bus_clk frequency still cannot go below 60Mhz in host mode, and this is not verified. A value of 2 can be chosen only if the pipe data width is 8 or 16 bits. In this case the when the ram_clk is switched to pipe_clk, it uses pipe_clk/2 instead of pipe_clk. If a value of 3 is chosen for RAMClkSel, then when ram_clk is switched to pipe_clk, then pipe_clk is used without any divider. - In device mode, when RAMClkSel != 2b00, the bus_clk_early frequency can be a minimum of 1 MHz. This is tested in simulation and also in hardware with Linux, Microsoft Windows 8, and MCCI Windows7 host drivers. Only control and non periodic transfers are supported when bus_clk is 1 MHz. For periodic applications, the bus_clk_early minimum frequency is higher depending on your application and SoC bus. Even though 1 MHz has been tested with standard host drivers, Synopsys recommends 5 MHz minimum for ASIC designs to provide a margin or at least have a backup option to increase the bus_clk frequency to 5 MHz if needed. Programming this field with random data will cause side effect. Bit Bash register testing is not recommended. |
| SCALEDOWN | 5:4 | rwNormal read/write | 0x0 | Scale-Down Mode (ScaleDown) When Scale-Down mode is enabled for simulation, the core uses scaled-down timing values, resulting in faster simulations. When Scale-Down mode is disabled, actual timing values are used. This is required for hardware operation. HS/FS/LS Modes - 2b00: Disables all scale-downs. Actual timing values are used. - 2b01: Enables scale-down of all timing values except Device mode suspend and resume. These include Speed enumeration, HNP/SRP, and Host mode suspend and resume - 2b10: Enables scale-down of Device mode suspend and resume timing values only. - 2b11: Enables bit 0 and bit 1 scale-down timing values. SS Mode - 2b00: Disables all scale-downs. Actual timing values are used. - 2b01: Enables scaled down SS timing and repeat values including: (1) Number of TxEq training sequences reduce to 8; (2) LFPS polling burst time reduce to 256 nS; (3) LFPS warm reset receive reduce to 30 uS. - 2b10: No TxEq training sequences are sent. Overrides Bit 4. - 2b11: Enables bit 0 and bit 1 scale-down timing values. |
| DISSCRAMBLE | 3 | rwNormal read/write | 0x0 | Disable Scrambling (DisScramble) Transmit request to Link Partner on next transition to Recovery or Polling. |
| U2EXIT_LFPS | 2 | rwNormal read/write | 0x1 | U2EXIT_LFPS If this bit is, - 0: the link treats 248ns LFPS as a valid U2 exit. - 1: the link waits for 8us of LFPS before it detects a valid U2 exit. This bit is added to improve interoperability with a third-party host/device controller. This host/device controller in U2 state while performing receiver detection generates an LFPS glitch of about 4ms duration. This causes the host/device to exit from U2 state because the LFPS filter value is 248ns. With the new functionality enabled, the host/device can stay in U2 while ignoring this glitch from the host/device controller. This bit is applicable for both host and device controller. This bit is added to improve interoperability with a third party host controller. This host controller in U2 state while performing receiver detection generates an LFPS glitch of about 4ms duration. This causes the device to exit from U2 state because the LFPS filter value is 248ns. With the new functionality enabled, the device can stay in U2 while ignoring this glitch from the host controller. |
| GblHibernationEn | 1 | rwNormal read/write | 0x0 | GblHibernationEn This bit enables hibernation at the global level. If hibernation is not enabled through this bit, the PMU immediately accepts the D0->D3 and D3->D0 power state change requests, but does not save or restore any core state. In addition, the PMUs never drive the PHY interfaces and let the core continue to drive the PHY interfaces. |
| DSBLCLKGTNG | 0 | rwNormal read/write | 0x0 | Disable Clock Gating (DsblClkGtng) This bit is set to 1 and the core is in Low Power mode, internal clock gating is disabled. You can set this bit to 1b1 after Power On Reset. |