CLK_CTRL1 (TTC) Register Description
| Register Name | CLK_CTRL1 |
|---|---|
| Relative Address | 0x0000000000 |
| Absolute Address |
0x00FF0E0000 (TTC0) 0x00FF0F0000 (TTC1) 0x00FF100000 (TTC2) 0x00FF110000 (TTC3) |
| Width | 7 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Clock Control register |
Alternate register name: Clock_Control_1
CLK_CTRL1 (TTC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Ex_E | 6 | rwNormal read/write | 0x0 | External Clock Edge: when this bit is set and the extend clock is selected, the counter clocks on the negative going edge of the external clock input. |
| C_Src | 5 | rwNormal read/write | 0x0 | 0: from 3-input mux (see LPD_IOP_SLCR.TTC_CLK_SEL) 1: EMIO: TTCx_CLK0 |
| PS_V | 4:1 | rwNormal read/write | 0x0 | Prescale value: 0: divide by 2 1: divide by 4 N: 2^(N+1) 15: 65536 Note: Prescaler must be enabled using [PS_En]. |
| PS_En | 0 | rwNormal read/write | 0x0 | Presscaler Enable: 0: disable 1: enable |