smmutbu3pcie_gicsw0_rd_I_main_QosGenerator_Bandwidth (FPD_INT_GPV) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

smmutbu3pcie_gicsw0_rd_I_main_QosGenerator_Bandwidth (FPD_INT_GPV) Register Description

Register Namesmmutbu3pcie_gicsw0_rd_I_main_QosGenerator_Bandwidth
Relative Address0x0000000A10
Absolute Address 0x00FD700A10 (FPD_INT_GPV)
Width32
TyperwNormal read/write
Reset Value0x00001000
Descriptionsmmutbu3pcie_gicsw0_rd_I_main_QosGenerator_Bandwidth

Alternate register name: if_smmutbu3pcie_gicsw0_rd_I_main_QosGenerator_Bandwidth

smmutbu3pcie_gicsw0_rd_I_main_QosGenerator_Bandwidth (FPD_INT_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
BANDWIDTH12:0rwNormal read/write0x1000Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words, the desired rate in MBps is divided by frequency in MHz of the NIU, and then multiplied by 256.