IPI1_ISR (IPI) Register Description
| Register Name | IPI1_ISR |
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| Relative Address | 0x0000040010 |
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| Absolute Address |
0x00FF340010 (IPI)
|
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| Width | 32 |
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| Type | wtcReadable, write a 1 to clear |
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| Reset Value | 0x00000000 |
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| Description | IPI1 Interrupt Status and Clear |
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The PSM target processor reads this register along with its mask register to determine which initiator(s) caused the IPI interrupt. READ: 0: inactive. 1: active. WRITE: 0: no effect. 1: clears this bit. Note: If a Status bit is 1 and its Mask is 0, then the interrupt signal is asserted to the target interrupt controller. Note: Beware that this does not provide the initiator with the state of the target's Mask register.
IPI1_ISR (IPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:10 | wtcReadable, write a 1 to clear | 0x0 | reserved |
| IPI6 | 9 | wtcReadable, write a 1 to clear | 0x0 | IPI6 without buffer |
| PMC_NOBUF | 8 | wtcReadable, write a 1 to clear | 0x0 | PMC without buffer |
| IPI5 | 7 | wtcReadable, write a 1 to clear | 0x0 | IPI5 |
| IPI4 | 6 | wtcReadable, write a 1 to clear | 0x0 | IPI4 |
| IPI3 | 5 | wtcReadable, write a 1 to clear | 0x0 | IPI3 |
| IPI2 | 4 | wtcReadable, write a 1 to clear | 0x0 | IP2 |
| IPI1 | 3 | wtcReadable, write a 1 to clear | 0x0 | IPI1 |
| IPI0 | 2 | wtcReadable, write a 1 to clear | 0x0 | IPI0 |
| PMC | 1 | wtcReadable, write a 1 to clear | 0x0 | PMC_IPI |
| PSM | 0 | wtcReadable, write a 1 to clear | 0x0 | PSM_IPI |