PCIE1_SMID_CFG1 (CPM5_SLCR_SECURE) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PCIE1_SMID_CFG1 (CPM5_SLCR_SECURE) Register Description

Register NamePCIE1_SMID_CFG1
Relative Address0x0000000214
Absolute Address 0x00FCDE0214 (CPM5_SLCR_SECURE)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000098
DescriptionSMID configuration for PCIe/DMA AXI Master 1 Interface to non coherent interconnect

PCIE1_SMID_CFG1 (CPM5_SLCR_SECURE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0Reserved
bdf_bit_sel_9 7:4rwNormal read/write0x9Determines which BDF bit drives SMID bit 9
bdf_bit_sel_8 3:0rwNormal read/write0x8Determines which BDF bit drives SMID bit 8