PMC_TAP_SLVERR_CTRL (PMC_JTAG_CSR) Register Description
| Register Name | PMC_TAP_SLVERR_CTRL |
|---|---|
| Relative Address | 0x000000001C |
| Absolute Address | 0x00F11A001C (PMC_JTAG_CSR) |
| Width | 1 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | APB slave error enable register |
PMC_TAP_SLVERR_CTRL (PMC_JTAG_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ENABLE | 0 | rwNormal read/write | 0x0 | Control to enable APB slave error generation. Programming this field with a value of 1 enables SLVERR during address decode failure. 0: SLVERR is disabled. For request address: Writes are ignored. Read returns 0. 1: SLVERR is enabled. For request address, SLVERR is asserted. Writes are ignored and read returns 0. |