PFx_PASID_CAP_EXEC_PERM_SUPP_1 (CPM4_PCIE0_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PFx_PASID_CAP_EXEC_PERM_SUPP_1 (CPM4_PCIE0_ATTR) Register Description

Register NamePFx_PASID_CAP_EXEC_PERM_SUPP_1
Relative Address0x0000000B10
Absolute Address 0x00FCA50B10 (CPM4_PCIE0_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPASID support for sending TLPS with Execute Requested bit.

This register should only be written to during reset of the PCIe block

PFx_PASID_CAP_EXEC_PERM_SUPP_1 (CPM4_PCIE0_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0PASID support for sending TLPS with Execute Requested bit.