SMMU_CB11_TLBIVAA_low (FPD_SMMU_TCU) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

SMMU_CB11_TLBIVAA_low (FPD_SMMU_TCU) Register Description

Register NameSMMU_CB11_TLBIVAA_low
Relative Address0x000002B608
Absolute Address 0x00FD82B608 (FPD_SMMU_TCU)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionInvalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.

SMMU_CB11_TLBIVAA_low (FPD_SMMU_TCU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Address31:0woWrite-only0x0Invalidates all of the unlocked TLB entries that match the VA provided as an argument, and the VMID of the context bank, regardless of the ASID. This operation includes global entries if appropriate.