PFx_SRIOV_SUPPORTED_PAGE_SIZE_1 (CPM4_PCIE1_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PFx_SRIOV_SUPPORTED_PAGE_SIZE_1 (CPM4_PCIE1_ATTR) Register Description

Register NamePFx_SRIOV_SUPPORTED_PAGE_SIZE_1
Relative Address0x0000000858
Absolute Address 0x00FCA60858 (CPM4_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPage Size Supported By Device: This field indicates the page sizes supported by the PF. This PF supports a page size of 2n+12 if bit n is Set

This register should only be written to during reset of the PCIe block

PFx_SRIOV_SUPPORTED_PAGE_SIZE_1 (CPM4_PCIE1_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x0Page Size Supported By Device: This field indicates the page sizes supported by the PF. This PF supports a page size of 2n+12 if bit n is Set