APB_IER (PMC_IOP_SLCR_SECURE) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

APB_IER (PMC_IOP_SLCR_SECURE) Register Description

Register NameAPB_IER
Relative Address0x000000004C
Absolute Address 0x00F107004C (PMC_IOP_SLCR_SECURE)
Width 1
TypewoWrite-only
Reset Value0x00000000
DescriptionAPB Interrupt Enable

Enable Interrupt Bits (write-only): 0: no effect 1: sets the mask bit = 0 (enables the interrupt signal) Note: Refer to the APB_ISR register for more information. Alternate register name: ier

APB_IER (PMC_IOP_SLCR_SECURE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err 0woWrite-only0x0Register address
decode error.