cmn4 (CPM5_INT_CSR) Register Description
| Register Name | cmn4 |
|---|---|
| Relative Address | 0x0000000130 |
| Absolute Address | 0x00FCA00130 (CPM5_INT_CSR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Routing bit Register to enable or disable routing of transactions from CPM to LPD or NoC via FPD |
cmn4 (CPM5_INT_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | rwNormal read/write | 0x0 | Setting this bit to 1b1 will make transactions from CPM Master to an LPD Slave port or NoC to be routed through FPD. This bit can be set for Coherency and Address translation purpose. If set to 1b0, transactions will not get diverted through FPD except transactions that explicitly are targeting an FPD Slave address region (0xA400_0000 - 0xBFFF_FFFF) |
| routing | 0 | rwNormal read/write | 0x0 | Setting this bit to 1b1 will make transactions from CPM Master to an LPD Slave port or NoC to be routed through FPD. This bit can be set for Coherency and Address translation purpose. If set to 1b0, transactions will not get diverted through FPD except transactions that explicitly are targeting an FPD Slave address region (0xA400_0000 - 0xBFFF_FFFF) |