| Field Name | Bits | Type | Reset Value | Description |
|---|
| Event0x12 | 17 | roRead-only | 0x1 | Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation. |
| Event0x11 | 16 | roRead-only | 0x1 | Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation. |
| Event0x10 | 15 | roRead-only | 0x0 | Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation. |
| Event0x0A | 9 | roRead-only | 0x1 | Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation. |
| Event0x09 | 8 | roRead-only | 0x1 | Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation. |
| Event0x08 | 7 | roRead-only | 0x0 | Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation. |
| Event0x01 | 1 | roRead-only | 0x1 | Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation. |
| Event0x00 | 0 | roRead-only | 0x1 | Provide the equivalent of the SMMU performance monitoring register map PMCEID0 register, in the register map of a translation context bank. Describes the event classes supported by the SMMU implementation. |