LL_REPLAY_FROM_RAM_PIPELINE (CPM4_PCIE1_ATTR) Register Description
| Register Name | LL_REPLAY_FROM_RAM_PIPELINE |
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| Relative Address | 0x0000000340 |
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| Absolute Address |
0x00FCA60340 (CPM4_PCIE1_ATTR)
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| Width | 32 |
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| Type | rwNormal read/write |
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| Reset Value | 0x00000000 |
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| Description | From Replay RAM Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on BRAM to Hard Block path (rdata). FALSE indicates that there is no pipeline. |
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This register should only be written to during reset of the PCIe block
LL_REPLAY_FROM_RAM_PIPELINE (CPM4_PCIE1_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
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| attr | 0 | rwNormal read/write | 0x0 | From Replay RAM Pipeline: If TRUE indicates presence of a external CLB flip-flop pipeline stage on BRAM to Hard Block path (rdata). FALSE indicates that there is no pipeline. |