attr_dma_pf_barlite_ext1 (CPM5_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

attr_dma_pf_barlite_ext1 (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_pf_barlite_ext1
Relative Address0x00000000C8
Absolute Address 0x00FCE100C8 (CPM5_DMA0_ATTR)
0x00FCE900C8 (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMap PFs and barhit to axi-lite master.
Everest hard ip does not have dedicated AXI-Lite master, so disabled with all 0.

This register should only be written to during reset of the PCIe block

attr_dma_pf_barlite_ext1 (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 5:0rwNormal read/write0x0Map PFs and barhit to axi-lite master.
Everest hard ip does not have dedicated AXI-Lite master, so disabled with all 0.