PFx_PRI_CAP_ON_7 (CPM5_PCIE_ATTR) Register Description
| Register Name | PFx_PRI_CAP_ON_7 |
|---|---|
| Relative Address | 0x0000001CE8 |
| Absolute Address |
0x00FCE09CE8 (CPM5_PCIE0_ATTR) 0x00FCE89CE8 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | PRI Capability Enable |
This register should only be written to during reset of the PCIe block
PFx_PRI_CAP_ON_7 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 | PRI Capability Enable |