PFx_PASID_CAP_PRIVIL_MODE_SUPP_15 (CPM5_PCIE_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)
Document ID
AM012
Release Date
2023-08-29
Revision
1.3

PFx_PASID_CAP_PRIVIL_MODE_SUPP_15 (CPM5_PCIE_ATTR) Register Description

Register NamePFx_PASID_CAP_PRIVIL_MODE_SUPP_15
Relative Address0x0000001FF4
Absolute Address 0x00FCE09FF4 (CPM5_PCIE0_ATTR)
0x00FCE89FF4 (CPM5_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPASID support for sending TLPs with Priviledge Mode Requested bit.

This register should only be written to during reset of the PCIe block

PFx_PASID_CAP_PRIVIL_MODE_SUPP_15 (CPM5_PCIE_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0PASID support for sending TLPs with Priviledge Mode Requested bit.