DEBUG_TL_SPARE (CPM4_PCIE1_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

DEBUG_TL_SPARE (CPM4_PCIE1_ATTR) Register Description

Register NameDEBUG_TL_SPARE
Relative Address0x0000000BA4
Absolute Address 0x00FCA60BA4 (CPM4_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTL Debug Spare Bits

This register should only be written to during reset of the PCIe block

DEBUG_TL_SPARE (CPM4_PCIE1_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr15:0rwNormal read/write0x0TL Debug Spare Bits