GICP1_IMR (PSM_GLOBAL) Register Description
| Register Name | GICP1_IMR |
|---|
| Relative Address | 0x0000002018 |
|---|
| Absolute Address |
0x00FFC92018 (PSM_GLOBAL)
|
|---|
| Width | 32 |
|---|
| Type | roRead-only |
|---|
| Reset Value | 0xFF3BFFFF |
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| Description | GIC Proxy Interrupt Mask Bank 1 |
|---|
Read-only. 0: enabled. 1: masked (disabled). If the status bit = 1 (asserted interrupt) and the mask bit = 0 (not masked), then the IRQ to the interrupt controllers is asserted. Software checks the ISR to determine the cause of the interrupt. Alternate register name: GICP1_IRQ_MASK
GICP1_IMR (PSM_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| src31 | 31 | roRead-only | 0x1 | LPD DMA channel 3 |
| src30 | 30 | roRead-only | 0x1 | LPD DMA channel 2 |
| src29 | 29 | roRead-only | 0x1 | LPD DMA channel 1 |
| src28 | 28 | roRead-only | 0x1 | LPD DMA channel 0 |
| src27 | 27 | roRead-only | 0x1 | GEM 1 Wake-up system interrupt |
| src26 | 26 | roRead-only | 0x1 | GEM 1 system interrupt |
| src25 | 25 | roRead-only | 0x1 | GEM 0 Wake-up system interrupt |
| src24 | 24 | roRead-only | 0x1 | GEM 0 system interrupt |
| src21 | 21 | roRead-only | 0x1 | SysMon |
| src20 | 20 | roRead-only | 0x1 | LPD Interconnect system interrupt |
| src19 | 19 | roRead-only | 0x1 | LPD XPPU |
| src17 | 17 | roRead-only | 0x1 | LPD SWDT interrupt |
| src16 | 16 | roRead-only | 0x1 | TTC 3, timer/clock 2 |
| src15 | 15 | roRead-only | 0x1 | TTC 3, timer/clock 1 |
| src14 | 14 | roRead-only | 0x1 | TTC 3, timer/clock 0 |
| src13 | 13 | roRead-only | 0x1 | TTC 2, timer/clock 2 |
| src12 | 12 | roRead-only | 0x1 | TTC 2, timer/clock 1 |
| src11 | 11 | roRead-only | 0x1 | TTC 2, timer/clock 0 |
| src10 | 10 | roRead-only | 0x1 | TTC 1, timer/clock 2 |
| src9 | 9 | roRead-only | 0x1 | TTC 1, timer/clock 1 |
| src8 | 8 | roRead-only | 0x1 | TTC 1, timer/clock 0 |
| src7 | 7 | roRead-only | 0x1 | TTC 0, timer/clock 2 |
| src6 | 6 | roRead-only | 0x1 | TTC 0, timer/clock 1 |
| src5 | 5 | roRead-only | 0x1 | TTC 0, timer/clock 0 |
| src4 | 4 | roRead-only | 0x1 | Inter-processor interrupt 6 |
| src3 | 3 | roRead-only | 0x1 | Inter-processor interrupt 5 |
| src2 | 2 | roRead-only | 0x1 | Inter-processor interrupt 4 |
| src1 | 1 | roRead-only | 0x1 | Inter-processor interrupt 3 |
| src0 | 0 | roRead-only | 0x1 | Inter-processor interrupt 2 |