PL_LANE4_CCIX_EDR_EQ_CONTROL (CPM5_PCIE_ATTR) Register Description
| Register Name | PL_LANE4_CCIX_EDR_EQ_CONTROL |
|---|---|
| Relative Address | 0x0000000338 |
| Absolute Address |
0x00FCE08338 (CPM5_PCIE0_ATTR) 0x00FCE88338 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Lane#4 CCIX EDR Equalization Control Register: Bit[3:0] - Downstream Port 20G Transmitter Preset Bit[11:8] - Upstream Port 20G Transmitter Preset Bit[19:16] - Downstream Port 25G Transmitter Preset Bit[27:24] - Upstream Port 25G Transmitter Preset |
This register should only be written to during reset of the PCIe block
PL_LANE4_CCIX_EDR_EQ_CONTROL (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 31:0 | rwNormal read/write | 0x0 | Lane#4 CCIX EDR Equalization Control Register: Bit[3:0] - Downstream Port 20G Transmitter Preset Bit[11:8] - Upstream Port 20G Transmitter Preset Bit[19:16] - Downstream Port 25G Transmitter Preset Bit[27:24] - Upstream Port 25G Transmitter Preset |