BANK_ECC_CE_ISR (XRAM_SLCR) Register Description
| Register Name | BANK_ECC_CE_ISR |
|---|---|
| Relative Address | 0x000000A060 |
| Absolute Address | 0x00FF95A060 (XRAM_SLCR) |
| Width | 32 |
| Type | wtcReadable, write a 1 to clear |
| Reset Value | 0x00000000 |
| Description | Status of the correctable ECC errors detected by XRAM banks |
BANK_ECC_CE_ISR (XRAM_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| BANK3 | 3 | wtcReadable, write a 1 to clear | 0x0 | A value of 1 in this register indicates that a correctable ECC error was detected by bank3. Program a value of 1 to clear this status. Refer to bank3 address space for more details on this ECC error. |
| BANK2 | 2 | wtcReadable, write a 1 to clear | 0x0 | A value of 1 in this register indicates that a correctable ECC error was detected by bank2. Program a value of 1 to clear this status. Refer to bank2 address space for more details on this ECC error. |
| BANK1 | 1 | wtcReadable, write a 1 to clear | 0x0 | A value of 1 in this register indicates that a correctable ECC error was detected by bank1. Program a value of 1 to clear this status. Refer to bank1 address space for more details on this ECC error. |
| BANK0 | 0 | wtcReadable, write a 1 to clear | 0x0 | A value of 1 in this register indicates that a correctable ECC error was detected by bank0. Program a value of 1 to clear this status. Refer to bank0 address space for more details on this ECC error. |