EDESR (DBG_A720_DBG) Register Description
| Register Name | EDESR |
|---|---|
| Relative Address | 0x0000000020 |
| Absolute Address | 0x00F0D00020 (DBG_APU0_DBG) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | External Debug Event Status Register |
EDESR (DBG_A720_DBG) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SS | 2 | rwNormal read/write | 0x0 | Halting step debug event pending. |
| RC | 1 | rwNormal read/write | 0x0 | Reset catch debug event pending. |
| OSUC | 0 | rwNormal read/write | 0x0 | OS unlock debug event pending. |