CTIINEN2 (DBG_CTI) Register Description
| Register Name | CTIINEN2 |
|---|---|
| Relative Address | 0x0000000028 |
| Absolute Address |
0x00F0CA0028 (DBG_APU_CTI) 0x00F0FD0028 (DBG_CPM_CTI) 0x00F0FA0028 (DBG_CPM_ELA_CTI) 0x00F0BD0028 (DBG_FPD_CTI) 0x00F0BC0028 (DBG_FPD_PSPL_CTI) 0x00F0BB0028 (DBG_FPD_SOC_CTI) 0x00F09D0028 (DBG_LPD_CTI) 0x00F08D0028 (DBG_PMC_CTI) 0x00F0A10028 (DBG_RPU0_CTI) 0x00F0A50028 (DBG_RPU1_CTI) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | CTI Trigger 2 to Channel Enable Register |
CTIINEN2 (DBG_CTI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TRIGINEN | 3:0 | rwNormal read/write | 0x0 | Enables a cross trigger event to the corresponding channel when an ctitrigin is activated. There is one bit of the field for each of the four channels.When a 1 is written to a bit in this register, it enables the ctitrigin signal to generate an event on the respective channel of the CTM. For example, TRIGINEN[0] set to 1 enables ctitrigin onto channel 0. Writing a 0 to any of the bits in this register disables the ctitrigin signal from generating an event on the respective channel of the CTM.Reading this register returns the programmed value. |