SD0_DDR50_Preset (PMC_IOP_SLCR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

SD0_DDR50_Preset (PMC_IOP_SLCR) Register Description

Register NameSD0_DDR50_Preset
Relative Address0x0000000438
Absolute Address 0x00F1060438 (PMC_IOP_SLCR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000002
DescriptionPreset Value for DDR50

Alternate register name: SD0_DDR50PRESET

SD0_DDR50_Preset (PMC_IOP_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:13razRead as zero0x0Reserved. Writes are ignored, read data is zero.
SD0_DDR50PRESET12:0rwNormal read/write0x2SD0 Preset Value for DDR50