EFuse_IDR (PMC_EFUSE_CTRL) Register Description
| Register Name | EFuse_IDR |
|---|---|
| Relative Address | 0x000000003C |
| Absolute Address | 0x00F124003C (PMC_EFUSE_CTRL) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | EFuse Interrupt Disable |
Disable the interrupt: 0: no effect 1: sets the mask bit = 1 Note: This register is write-only. Note: Writes can be disabled with Write_Lock register. Alternate register name: eFuse_idr
EFuse_IDR (PMC_EFUSE_CTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| APB_Error | 31 | woWrite-only | 0x0 | APB program interface error Note: Field name reference: apb_slverr |
| Reserved | 30:15 | woWrite-only | 0x0 | reserved |
| Cache_Parity_E2 | 14 | woWrite-only | 0x0 | Cache Page2 Parity Error |
| Cache_Parity_E1 | 13 | woWrite-only | 0x0 | Cache Page1 Parity Error |
| Cache_Parity_E0S | 12 | woWrite-only | 0x0 | Cache Page0 SRAM Parity Error |
| Cache_Parity_E0R | 11 | woWrite-only | 0x0 | Cache Page0 Register Parity Error |
| Cache_APB_Error | 10 | woWrite-only | 0x0 | APB programming interface error in cache-register domain Note: Field name reference: CACHE_APB_SLVERR |
| Cache_Req_Error | 9 | woWrite-only | 0x0 | RD or CacheReload Request when Cache-FSM is not in IDLE |
| Main_Req_Error | 8 | woWrite-only | 0x0 | PGM or RD Request when Main-FSM is not in IDLE. |
| Read_on_Cache_Ld | 7 | woWrite-only | 0x0 | APB Read or HWTstBits Write to SRAM-cache during Cache-load. |
| Cache_FSM_Error | 6 | woWrite-only | 0x0 | Invalid state in Cache FSM |
| Main_FSM_Error | 5 | woWrite-only | 0x0 | Invalid state in Main FSM |
| Cache_Error | 4 | woWrite-only | 0x0 | Parity error in the EFuse cache |
| Rd_Error | 3 | woWrite-only | 0x0 | RD was requested to a restricted fuse |
| Rd_Done | 2 | woWrite-only | 0x0 | RD operation completed |
| Pgm_Error | 1 | woWrite-only | 0x0 | PGM was requested to a restricted fuse |
| Pgm_Done | 0 | woWrite-only | 0x0 | PGM operation has completed |