LPD_AXI_RPU0 (LPD_INT_CSR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

LPD_AXI_RPU0 (LPD_INT_CSR) Register Description

Register NameLPD_AXI_RPU0
Relative Address0x0000090000
Absolute Address 0x00FE690000 (LPD_INT_CSR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000016
DescriptionTimeout, Idle, and Reset control: LPD main switch ePort to RPU0 memory and configuration (AXI ProgIF)

Alternate register name: intlpd_rpu0_axi

LPD_AXI_RPU0 (LPD_INT_CSR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:5rwNormal read/write0x0
Sw_Reset 4rwNormal read/write0x1Reset for ePort (active-Low):
0: Port held in reset mode
1: Port reset de-asserted
Note: Put the port connection into its idle state before asserting reset.
Note: Field name reference: raw_rst_n
Idle_Req 3rwNormal read/write0x0Send idle/isolation and wakeup request to the ePort:
0: Send wake-up request
1: Send idle and isolation request
Note: Field name reference: power_idlereq
Idle_Ack 2roRead-only0x1Idle request acknowledgement from ePort:
0: Idle state request not detected
1: Idle state request detected or the port is transitioning between idle and active.
Note: This bit is High from the time the idle request is made until the idle state is obtained. The [idle_ack] and [idle] bits can be monitored to determine the exact statue of the port.
Note: Field name reference: power_idleack
Idle 1roRead-only0x1Idle status of ePort:
0: port is active
1: port is inactive
Note: When inactive, a transaction to the programming interface address range will return the address decode error signal, DECERR.
Note: Field name reference: power_idle
Timeout_En 0rwNormal read/write0x0Enable timeout counter:
0: disable counter
1: enable counter
Note: The timeout counter must be enabled to generate a timeout interrupt.
Note: Field name reference: mainexten