DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FLD (CPM4_PCIE1_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FLD (CPM4_PCIE1_ATTR) Register Description

Register NameDEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FLD
Relative Address0x0000000B84
Absolute Address 0x00FCA60B84 (CPM4_PCIE1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionWhen set to FALSE, a dynamic deskew failure will cause Recovery, otherwise, if set to TRUE, dynamic deskew failure will be ignored. Should be set to FALSE on Asynchronous Links. May have to be set to TRUE on Synchronous Link with BER to avoid unnecessary transitions to Recovery.

This register should only be written to during reset of the PCIe block

DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FLD (CPM4_PCIE1_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 0rwNormal read/write0x0When set to FALSE, a dynamic deskew failure will cause Recovery, otherwise, if set to TRUE, dynamic deskew failure will be ignored. Should be set to FALSE on Asynchronous Links. May have to be set to TRUE on Synchronous Link with BER to avoid unnecessary transitions to Recovery.