CLKMON7_CTRL (CRP) Register Description
| Register Name | CLKMON7_CTRL |
|---|---|
| Relative Address | 0x00000002DC |
| Absolute Address | 0x00F12602DC (CRP) |
| Width | 11 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000400 |
| Description | ClkMon Control, Channel 7 |
Select the base clock using [BaseClk_Sel]. Select the clock to monitor using the [Mon_Sel]. Enable the clock monitor with [Enable] and set either [Start_Continuous] or [Start_Single] = 1. Alternate register name: CHKR7_CTRL
CLKMON7_CTRL (CRP) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Idle_State | 10 | roRead-only | 0x1 | ClkMon state: 0: active 1: idle Note: Read this bit when both start bits are = 0. |
| Start_Single | 9 | rwNormal read/write | 0x0 | Trigger ClkMon to monitor the selected clock once: 0: disabled 1: trigger one monitoring event Note: This bit is self-clearing. |
| Start_Continuous | 8 | rwNormal read/write | 0x0 | Trigger ClkMon to repeatedly monitor the selected clock: 0: disable; stop continous clock monitoring 1: enable continous clock monitoring |
| Reserved | 7 | rwNormal read/write | 0x0 | reserved |
| BaseClk_Sel | 6 | rwNormal read/write | 0x0 | Select the base clock source: 0: REF_CLK pin 1: PMC_IRO_CLK Note: Field name reference: clkb_mux_ctrl |
| Reserved | 5 | rwNormal read/write | 0x0 | reserved |
| Monitor_Sel | 4:1 | rwNormal read/write | 0x0 | Select the clock to monitor: LPD Clocks: 0000: RPU_REF_CLK 0001: LPD_TOPSW_CLK 0010: LPD_LSBUS_CLK 0011: LPD_SWDT_REF_CLK 0100: LPD_DMA_REF_CLK 0101: PSM_REF_CLK FPD Clocks: 0110: APU0_REF_CLK (divided by 4) 0111: APU1_REF_CLK (divided by 4) 1000: FPD_TOPSW_CLK 1001: FPD_LSBUS_CLK 1010: FPD_SWDT_CLK PMC Clocks: 1011: PMC_IRO_CLK 1100: PMC_LSBUS_CLK 1101: NOC_REF_CLK (divided by 4) 1110: NPI_REF_CLK 1111: REF_CLK pin Note: Field name reference: clka_mux_ctrl |
| Enable | 0 | rwNormal read/write | 0x0 | ClkMon enable: 0: disable 1: enable |