attr_dma_pciebar2axibar_pf1_bar1_sec_cache_len (CPM5_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

attr_dma_pciebar2axibar_pf1_bar1_sec_cache_len (CPM5_DMA_ATTR) Register Description

Register Nameattr_dma_pciebar2axibar_pf1_bar1_sec_cache_len
Relative Address0x00000003F4
Absolute Address 0x00FCE103F4 (CPM5_DMA0_ATTR)
0x00FCE903F4 (CPM5_DMA1_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
Descriptionattr_dma_pciebar2axibar_pf1_bar1_sec_cache_len

This register should only be written to during reset of the PCIe block

attr_dma_pciebar2axibar_pf1_bar1_sec_cache_len (CPM5_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
len 6:0rwNormal read/write0x0Bar size in bits for PF[*] BAR