BLOCK_GAP_CTRL (SD_eMMC) Register Description
| Register Name | BLOCK_GAP_CTRL |
|---|---|
| Relative Address | 0x000000002A |
| Absolute Address |
0x00F104002A (SD_eMMC0) 0x00F105002A (SD_eMMC1) |
| Width | 8 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000080 |
| Description | This register is used to program the block gap request, read wait control and interrupt at block gap |
Software Driver name: XSDPS_BLK_GAP_CTRL Alternate register name: reg_blockgapcontrol
BLOCK_GAP_CTRL (SD_eMMC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| BootAckEn | 7 | rwNormal read/write | 0x1 | To check for the boot acknowledge in boot operation. 0 Will not wait for boot ack from eMMC card, 1 Wait for boot ack from eMMC card Note: Field name reference: blkgapctrl_bootackena |
| AltBootMode | 6 | rwNormal read/write | 0x0 | To start boot code access in alternative mode. 0 To stop alternative boot mode access, 1 To start alternative boot mode access Note: Field name reference: blkgapctrl_altbootmode |
| BootEn | 5 | rwNormal read/write | 0x0 | To start boot code access. 0 To stop boot code access, 1 To start boot code access Note: Field name reference: blkgapctrl_bootenable |
| BG_Intr | 3 | rwNormal read/write | 0x0 | This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. Note: Field name reference: blkgapctrl_interrupt |
| RdWait | 2 | rwNormal read/write | 0x0 | The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the card does not support read wait, this bit shall never be set to 1 otherwise DAT line conflict may occur. If this bit is set to 0, Suspend / Resume cannot be supported. 0 Disable Read-Wait Control 1 Enable Read-Wait Control Note: Field name reference: blkgapctrl_rdwaitctrl |
| Continue | 1 | wtcReadable, write a 1 to clear | 0x0 | This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0 and set this bit to restart the transfer. The HC automatically clears this bit in either of the following cases: 1) In the case of a read transaction, the DAT Line Active changes from 0 to 1 as a read transaction restarts. 2) In the case of a write transaction, the Write transfer active changes from 0 to 1 as the write transaction restarts. Therefore it is not necessary for Host driver to set this bit to 0. If Stop At Block Gap Request is set to 1, any write to this bit is ignored. 0 Ignore 1 Restart Note: Field name reference: blkgapctrl_continue |
| Stop_Req | 0 | rwNormal read/write | 0x0 | This bit is used to stop executing a transaction at the next block gap for non- DMA,SDMA and ADMA transfers. Until the transfer complete is set to 1, indicating a transfer completion the HD shall leave this bit set to 1. Clearing both the Stop At Block Gap Request and Continue Request shall not cause the transaction to restart. Read Wait is used to stop the read transaction at the block gap. The HC shall honour Stop At Block Gap Request for write transfers, but for read transfers it requires that the SD card support Read Wait. Therefore the HD shall not set this bit during read transfers unless the SD card supports Read Wait and has set Read Wait Control to 1. In case of write transfers in which the HD writes data to the Buffer Data Port register, the HD shall set this bit after all block data is written. If this bit is set to 1, the HD shall not write data to Buffer data port register. This bit affects Read Transfer Active, Write Transfer Active, DAT line active and Command Inhibit (DAT) in the Present State register. 0 Transfer 1 Stop Note: Field name reference: blkgapctrl_stopatblkgap |