ADV_SWTm_BAR4_CONTROL_3 (CPM5_PCIE_ATTR) Register Description
| Register Name | ADV_SWTm_BAR4_CONTROL_3 |
|---|---|
| Relative Address | 0x00000023DC |
| Absolute Address |
0x00FCE0A3DC (CPM5_PCIE0_ATTR) 0x00FCE8A3DC (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | BAR4 Control - Specifies the configuration of BAR 4. For Endpoint, the various encodings are: 000: Disabled 001: 32-bit IO BAR 010-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable 110: Part of 64-bit memory BAR 4-5, non-prefetchable 111: Part of 64-bit memory BAR 4-5, prefetchable For non-Endpoint (Type 1) Config Space, the Memory Base & Limit encodings are: 000: Disabled (RO) 001: Enabled (RW) 010-111: Reserved |
This register should only be written to during reset of the PCIe block
ADV_SWTm_BAR4_CONTROL_3 (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 2:0 | rwNormal read/write | 0x0 | BAR4 Control - Specifies the configuration of BAR 4. For Endpoint, the various encodings are: 000: Disabled 001: 32-bit IO BAR 010-011: Reserved 100: 32-bit memory BAR, non-prefetchable 101: 32-bit memory BAR, prefetchable 110: Part of 64-bit memory BAR 4-5, non-prefetchable 111: Part of 64-bit memory BAR 4-5, prefetchable For non-Endpoint (Type 1) Config Space, the Memory Base & Limit encodings are: 000: Disabled (RO) 001: Enabled (RW) 010-111: Reserved |