PL_SIM_FAST_LINK_TRAINING (CPM5_PCIE_ATTR) Register Description
| Register Name | PL_SIM_FAST_LINK_TRAINING |
|---|---|
| Relative Address | 0x0000000230 |
| Absolute Address |
0x00FCE08230 (CPM5_PCIE0_ATTR) 0x00FCE88230 (CPM5_PCIE1_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Fast Link Training for Simulations: Link training time is shortened to facilitate fast simulation of the design. Enabling this bit has the following effects: 1. When PL_SIM_FAST_LINK_TRAINING[0] = 1b, all 1 ms, 2 ms, 12 ms, 24 ms, 32 ms and 48 ms timeout intervals in the LTSSM are shortened by a factor of 512. 2. When PL_SIM_FAST_LINK_TRAINING[1] = 1b, in the Polling.Active, Recovery.RecLock (Ext Sync Enabled) state of the LTSSM, only 16 training sequences are required to be transmitted (Instead of 1024) to make the transition to the Configuration state. Must be set to 00b for non-simulation use. |
This register should only be written to during reset of the PCIe block
PL_SIM_FAST_LINK_TRAINING (CPM5_PCIE_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 1:0 | rwNormal read/write | 0x0 | Fast Link Training for Simulations: Link training time is shortened to facilitate fast simulation of the design. Enabling this bit has the following effects: 1. When PL_SIM_FAST_LINK_TRAINING[0] = 1b, all 1 ms, 2 ms, 12 ms, 24 ms, 32 ms and 48 ms timeout intervals in the LTSSM are shortened by a factor of 512. 2. When PL_SIM_FAST_LINK_TRAINING[1] = 1b, in the Polling.Active, Recovery.RecLock (Ext Sync Enabled) state of the LTSSM, only 16 training sequences are required to be transmitted (Instead of 1024) to make the transition to the Configuration state. Must be set to 00b for non-simulation use. |