mcap1_intcpm_axi_power_main_ResilienceFaultController_IntClr (CPM5_INT_GPV) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

mcap1_intcpm_axi_power_main_ResilienceFaultController_IntClr (CPM5_INT_GPV) Register Description

Register Namemcap1_intcpm_axi_power_main_ResilienceFaultController_IntClr
Relative Address0x0000001830
Absolute Address 0x00FCD81830 (CPM5_INT_GPV)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionInterruptClear register

Alternate register name: if_mcap1_intcpm_axi_power_main_ResilienceFaultController_IntClr

mcap1_intcpm_axi_power_main_ResilienceFaultController_IntClr (CPM5_INT_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MissionFaultClr 1wtcReadable, write a 1 to clear0x0Clear Mission Fault
LatentFaultClr 0wtcReadable, write a 1 to clear0x0Clear Latent Fault